Semiconductor device and method for producing same

ABSTRACT

A Metal Oxide Semiconductor (MOS) cell design has traditional planar cells extending in a first dimension, and trenches with their length extending in a third dimension, orthogonal to the first dimension in a top view. The manufacturing process includes forming a horizontal channel, and a plurality of trenches discontinued in the planar cell regions. Horizontal planar channels are formed in the mesa of the orthogonal trenches. A series connected horizontal planar channel and a vertical trench channel are formed along the trench regions surrounded by the first base. The lack of a traditional vertical channel is important to avoid significant reliability issues (shifts in threshold voltage Vth). The planar cell design offers a range of advantages both in terms of performance and processability. Manufacture of the planar cell is based on a self-aligned process with minimum number of masks, with the potential of applying additional layers or structures.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority to GB Patent Application No.1911357.0 filed on 8 Aug. 2019. The entirety of this application ishereby incorporated by reference for all purposes.

TECHNICAL FIELD

The invention relates to the field of power semiconductor devices. Itrelates to a power semiconductor device with layers of differentconductivity types and a method for producing such a semiconductordevice.

BACKGROUND

Planar and Trench MOS cell designs exhibit a number of advantages anddisadvantages for IGBT and MOSFET designs. For IGBTs, typical Planar andTrench designs are shown in FIGS. 1A and 2A. Both designs canincorporate an enhancement n-type layer for improved excess carrierstorage as shown in FIGS. 1B and 2B.

FIG. 1A shows a prior art IGBT with planar gate electrodes. The IGBT 200is a device with a four-layer structure, which are arranged between anemitter electrode 3 on an emitter side 31 and a collector electrode 2 ona collector side 21, which is arranged opposite of the emitter side 31.An (n-) doped drift layer 4 is arranged between the emitter side 31 andthe collector side 21. A p doped planar base layer 9 is arranged betweenthe drift layer 4 and the emitter electrode 3, which planar base layer 9is in direct electrical contact to the emitter electrode 3. A planarn-doped source region 7 is arranged on the emitter side 31 embedded intothe planar base layer 9 and contact opening 14 to the emitter electrode3. In addition, a planar p doped region 8 arranged on the emitter side31 below region 7 and embedded into the planar base layer 9 and contactopening 14 through region 7 and extending to region 8 is formed for theemitter electrode 3.

A planar gate electrode 10 is arranged on top of the emitter side 31.The planar gate electrode 10 is electrically insulated from the planarbase layer 9, the planar source region 7 and the drift layer 4 by aplanar insulating layer 12. There is a further insulating layer 13arranged between the planar gate electrode 10 and the emitter electrode3.

The planar cell concept offers a lateral MOS channel 15 which suffersfrom non-optimal charge spreading (so called JFET effect) near the cellresulting in low carrier enhancement and higher conduction losses.Furthermore, due to the lateral channel design, the planar cell designsuffers also from the PNP bipolar transistor hole drain effect (PNPeffect) due to the bad spreading of electrons flowing out of the MOSchannel. However, the accumulation layer between the MOS cells offersstrong charge enhancement for the PIN diode part (PIN effect). Theplanar design also requires more area resulting in less cell packingdensity for reduced channel resistance.

On the other hand, the planar design provides good blocking capabilitydue to low peak fields at the cell and in between. The planar design canalso provide good controllability and low switching losses and the celldensities in planar designs are easily adjusted for the required shortcircuit currents. Due to the fact that there exist few high peakelectric fields in the gate oxide regions, the planar design offers goodreliability with respect to parameter shifting during operation underhigh voltages. Also, the introduction of enhanced layers in planar cellsas shown in FIG. 1B has resulted in lower losses rivalling thoseachieved with trench designs as explained below.

The trench cell concept for a trench IGBT 300 shown in FIG. 2B offers avertical MOS channel 16 which provides enhanced injection of electronsin the vertical direction and suffer from no drawbacks from chargespreading (JFET effect) near the cell. Therefore, the trench cells showmuch improved carrier enhancement for lower conduction losses. Due tothe vertical channel design, the trench offers also less hole draineffect (PNP effect) due to the improved electron spreading out of theMOS channel. Modern trench designs adopting mesa widths (trench totrench distance) below 1 μm achieve very low conduction losses sinceclosely packed trenches can provide a strong barrier to hole drainage.Matching such a performance with less complex processes can be of agreat advantage. The accumulation layer at the bottom of the trenchoffers strong charge enhancement for the PIN diode part. Hence wideand/or deep trenches show optimum performance. Furthermore, the trenchdesign offers large cell packing density for reduced channel resistance.

However, the trench design suffers from lower blocking capability nearthe bottom corners of the trenches due to high peak electric fields.This has also resulted in parameter shifting during operation due to hotcarrier injection into the gate oxide. The trench design has also alarge MOS accumulation region and associated capacitance resulting inbad controllability and high switching losses. The high cell densitiesin trench designs will also result in high short circuit currents.Finally, gate parameter shifts can occur under normal gate biasingstress conditions due to the trench etch process in relation to thesilicon crystal orientation and the critical region at the n-source andp-base junction which is formed at the trench gate oxide 12′ and definesthe device MOS parameters.

Hence, optimizing the trench design to overcome the above drawbacks hasnormally resulted in higher losses when compared to the initial lossestimations and potential of trench designs. Many trench designs havebeen proposed with particular focus on the regions between the activeMOS cells for lowering the losses and improving the devicecontrollability. Another approach in previous inventions combines planarand trench designs. This was proposed to obtain the advantage of theplanar designs (region between the cells) and trench designs (the cell)while eliminating some of the drawbacks of the planar and trenchdesigns.

In U.S. Pat. No. 9,064,925B2, the Trench Planar IGBT 600 shown in FIG. 3combines both a planar and trench MOS cells in a single design. However,both the planar channel 15 and trench channel 16 are separated.Similarly, in “Trench emitter IGBT with lateral and vertical MOSchannels” (Proc. 23rd Internat. Conf. on Microelectronics MIEL 2002,163-166) an IGBT is described, which comprises trench gate electrodesand planar gate electrodes in one device.

Zeng et al., Numerical Analysis of a Trench VDMOST Structure With NoQuasi-Saturation (Solid State Electronics, V38, No 4, page 821-828,1995) represents the first publication of Trench Planar MOS cell design.A similar design was published as a Spulber et al., A Novel GateGeometry for the IGBT: The Trench Planar Insulated Gate BipolarTransistor (TPIGBT) (IEEE Electron Device Letters, Vol 20, No. 11,November 1999, page 580). The Trench Planar IGBT 400 design shown inFIG. 4A consist only of a planar channel and proposes a trench structureto improve carrier accumulation. The concept proposed shallow trenchesfor improved blocking capability. In U.S. Pat. No. 9,093,522B2, asimilar Trench Planar design 401 with an enhancement layer 17 describedwith an embodiment where the channel extends to include trench section16 as shown in FIG. 4B. The channels are formed with a gaussian dopingprofile with the maximum doping region near the n-source p-base junctionwhich defines the device MOS parameter. Hence, the trench channel willbe very lightly doped and will have little impact on the deviceoperation. In U.S. Pat. No. 8,441,046B2, A Planar Trench MOS IGBT 500with an enhancement layer was described as shown in FIG. 5. Similar tothe Trench Planar NOS cell described above, the Planar Trench designincludes a planar channel 15 and a trench channel 16 with the trenchchannel having higher doping levels compared to the Trench Planardesign. U.S. Pat. No. 8,441,046B2 also describes a Trench ShieldedPlanar version where the trench is grounded (not connected to the gate)and in one version cuts orthogonally through the planar cell.

The majority of the above patents describe an active trench connected tothe gate in combination with a planar channel in a two-dimensionalarrangement.

In U.S. Pat. No. 6,380,586B1 describes a trench IGBT 700 where planarchannels 15 are orthogonally positioned in relation to the trenchregions as shown in FIG. 6 for an embodiment having a discontinuedtrench at the emitter contact 3. A continuous trench cutting through theemitter contact 3 was also described. The main feature of this structureis the trench channel 16 which will provide electron injection in bothlateral and vertical dimensions at the trench wall as shown in thecross-section B-B′ as shown in FIG. 7. Such a device will have differentMOS parameters such as the threshold voltage for the vertical andlateral channels. Furthermore, for the discontinued version, the trenchMOS channel 16 at the trench periphery near 10′ can become critical dueto the sharp trench curvature in that region.

To overcome the above issues, U.S. Pat. No. 9,640,644 describes a planarcell structure 800 where the n-source regions 7 are separated from thetrench by a highly doped p-region 8 which also extend along the trenchorthogonal dimension for achieving higher turn-off capability as shownin FIG. 8. Hence, only a planar channel 15 is formed in this structureand no vertical channel along the trench oxide 12′ is present as shownin FIG. 9 for the cross-section B-B′. However, this device will notprovide lower conduction losses and the highly doped p-regions canresult in high hole drainage levels.

The structures described above also suffer from complex and criticalalignment process steps such as n-source 7 and p-region 8 structuringwhich can also increase the cost and limit the option to reduce the celldimensions for providing lower losses.

It is desirable to find a new MOS cell design concept that can stillbenefit from the combination of the trench and planar MOS cell conceptswhile enabling simple process steps and lower conduction/on-statelosses.

SUMMARY

A Planar Insulated Gate Bipolar Transistor IGBT with improved electricalcharacteristics is provided. Furthermore, a method for producing such aplanar semiconductor device is also provided.

It is an object of the invention to provide a power semiconductor devicewith reduced on-state losses, low drainage of holes, stable gateparameters, improved blocking capability, and good controllability.

The power semiconductor device has layers of different conductivitytypes, which layers are arranged between an emitter electrode on anemitter side and a collector electrode on a collector side, which isarranged opposite of the emitter side. The layers comprise:

-   -   a drift layer of a first conductivity type, which is arranged        between the emitter side and the collector side, separated in        the second dimension    -   a first base layer of a second conductivity type, which is        arranged between the drift layer and the emitter electrode,        which first base layer extends in the first dimension    -   a source region of the first conductivity type, which is        arranged at the emitter side embedded into the first base layer        and contacts the emitter electrode, which source region has a        higher doping concentration than the drift layer, and extends in        the first dimension, and extends in the third dimension to the        first gate electrode,    -   a second base layer of the second conductivity type, which is        arranged at the emitter side embedded into the first base layer        and is situated deeper than the source region, and contacts the        emitter electrode, which second base layer region has a higher        doping concentration than the first base layer,    -   a first gate electrode, which is arranged on top of the emitter        side and the first gate electrode is electrically insulated from        the first base layer, the source region and the drift layer by a        first insulating layer, an lateral/horizontal channel is        formable between the emitter electrode, the first source region,        the first base layer and the drift layer when a positive voltage        bias is applied to the first gate electrode    -   a plurality of trenches embedding second gate electrodes, each        of which is electrically insulated from the first base layer and        the drift layer by a second insulating layer and which trenches        are arranged with their length parallel to the third dimension        (ie. orthogonally to the first direction in a top view plane),        and are discontinued in the planar channel regions and extend        deeper into the drift layer than the first base layer, a        vertical channel is formable between the lateral/horizontal        channel, the first base layer and the drift layer when a        positive voltage bias is applied to the second gate electrodes.

The planar semiconductor device includes planar cells with a lateral orhorizontal channel and a plurality of trenches, which are arrangedorthogonally to the longitudinal extension direction of the planar cellsand are discontinued in the planar channel regions to formlateral/horizontal planar channels in the mesa regions between thetrenches, and form exceptionally a series connection between alateral/horizontal planar channel and a vertical trench channel only inthe discontinued trench regions.

The planar semiconductor device integrates a Trench into a Planar MOScell in order to gain the advantages of both designs in terms of reducedon-state losses, low drainage of holes, stable gate parameters, improvedblocking and good controllability.

The advantage of the planar gate design and trench design can becombined in the inventive semiconductor device while the disadvantagesof the planar cell region and inter-space between trench cells areeliminated.

Due to the fact that the area in between the orthogonal gate trenchesdoes not need to be further structured, very high-density trenches canbe used with trench mesa dimensions below 100 nm. This willsignificantly reduce the hole drainage effect as well known to thoseexperts in the field.

In addition, for discontinued orthogonal gate trenches at the planarcell, the trench mesa dimension at the planar cell can be reduced to 1μm for further reducing the hole drainage effect while keeping theplanar cell dimensions larger than 1 μm.

The planar source region is formed to ensure stable gate parameters andblocking capability. However, the trenches will provide a verticalchannel with improved vertical spreading.

Some or all of the plurality of second gate electrodes can be directlyconnected to the first gate electrodes, or can be grounded to theemitter electrode, or made floating. If the second gate electrodes gatesare shorted to the emitter electrode, there is no voltage differentialbetween the second gate electrodes and effectively no capacitance. Sincethe second gates do not invert the first base region, the cellcontaining the second gate is a passive type of cell, as opposed to anactive cell controlled by the gate trenches. By controlling the numberof passive cells, the input capacitance of the device can be preciselycontrolled.

Similarly, if the second gate electrodes are floating, resulting in apassive cell, the potential floats up to the emitter voltage so there iseffectively no capacitance associated with the second gates.

Furthermore, the device is easy to manufacture, because the inventivedesign can be manufactured based on a self-aligned process with minimuma number of masks required.

The new design offers a wide range of advantages both in terms ofperformance (reduced losses, improved controllability and reliability),and processability (very narrow mesa design rules, reliable planarprocess compatibility) with the potential of applying enhanced layerstructures. The inventive design is suitable for full or part stripesbut can also be implemented in cellular designs.

The design is also suitable for reverse conducting structure and can beapplied to both IGBTs and MOSFETs based on silicon or wide bandgapmaterials such as Silicon Carbide SiC.

The method for manufacturing a power semiconductor device comprises thefollowing steps:

-   -   a trench region is produced by etching on the first main side of        the substrate of a first conductivity type    -   a first oxide layer is produced on a first main side of a        substrate of a first conductivity type,    -   a structured gate electrode layer with at least one opening is        produced on the first main side on top of the first oxide layer,    -   first dopants of a second conductivity type are implanted into        the substrate on the first main side and,    -   the first dopants are diffused into the substrate, characterized        in that,    -   the structured gate electrode layer is used as a mask for        implanting the first dopants,    -   second dopants of a first conductivity type are implanted into        the substrate on the first main and,    -   the second dopants are diffused into the substrate,        characterized in that,    -   the second dopants are diffused to a lower depth than the first        dopants,    -   the structured gate electrode layer or an additional mask is        used as a mask for implanting the second dopants,    -   third dopants of a second conductivity type are implanted into        the substrate on the first main side and,    -   the third dopants are diffused into the substrate, characterized        in that,    -   the third dopants are implanted and diffused to a lower depth        than the first dopants,    -   the structured gate electrode layer or an additional mask is        used as a mask for implanting the third dopants,    -   an insulating oxide layer is produced on the first main side,    -   a contact opening is produced by etching through the insulating        layer and by filling a resulting contact opening with metal

The method for manufacturing a power semiconductor device, in particularan IGBT or MOSFET, has the advantage that the base and source layers areself-aligned by using the structured gate electrode layer as a mask.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be explained in more detail in the following textwith reference to the attached drawings, in which:

FIGS. 1A-B: show the cross sections of Planar MOS IGBT structures (priorart).

FIGS. 2A-B: show the cross sections of Trench MOS IGBT structures (priorart).

FIG. 3: show the cross section of Trench Planar MOS IGBT structure(prior art).

FIGS. 4A-B: show an alternative cross-section of Trench Planar MOS IGBTstructures (prior art).

FIG. 5A-B: show the cross sections of Planar Trench MOS IGBT structures(prior art).

FIG. 6: show the Trench Planar MOS IGBT structure (prior art).

FIG. 7: show the cross sections of Trench Planar MOS IGBT structure atcut B (prior art).

FIG. 8: show the Trench MOS IGBT structure (prior art).

FIG. 9: show the cross sections of Trench MOS IGBT structure at cut B(prior art).

FIG. 10: show a first exemplary embodiment of a power semiconductordevice according to the invention.

FIG. 11: Top view of first exemplary embodiment of a punch-through IGBTaccording to the invention.

FIG. 12: Cross section along A-A′ of first exemplary embodiment of apunch-through IGBT according to the invention.

FIG. 13: Cross section along B-B′ of first exemplary embodiment of apunch-through IGBT according to the invention.

FIG. 14: Cross section along C-C′ of first exemplary embodiment of apunch-through IGBT according to the invention showing series connectedplanar and trench channels.

FIG. 15A: A typical top view for a stripe design of first exemplaryembodiment of a punch-through IGBT according to the invention where alltrenches have the same length

FIG. 15B: A typical top view for a stripe design of first exemplaryembodiment of a punch-through IGBT according to the invention where someof the trenches have different lengths

FIGS. 16-24: show a cross section of the different steps of the methodfor manufacturing a semiconductor device according to the invention.

FIGS. 25-31: show a top view of the different steps of the method formanufacturing a semiconductor device according to the invention.

FIG. 32: second exemplary embodiment of a punch through IGBT withextended second base layer under the source region and etched contactthrough the source region according to the invention.

FIG. 33: third exemplary embodiment of a reverse conducting IGBTaccording to the invention.

FIG. 34: fourth exemplary embodiment of a punch through IGBT withn-enhancement layer according to the invention

DETAILED DESCRIPTION

It should be noted that the drawings are only schematic and not toscale. Generally, alike or alike-functioning parts are given the samereference symbols. The described embodiments are meant as examples andshall not confine the invention.

FIG. 10 shows a first exemplary embodiment of a power semiconductordevice 1 in form of a punch through insulated gate bipolar transistor(IGBT) with a four-layer structure (pnpn). The layers are arrangedbetween an emitter electrode 3 on an emitter side 31 and a collectorelectrode 2 on a collector side 21, which is arranged opposite of theemitter side 31. The IGBT comprises the following layers:

an (n-) doped drift layer 4, which is arranged between the emitter side31 and the collector side 21, extending in a second dimension Y

a p doped first base layer 9, which is arranged between the drift layer4 and the emitter electrode 3, extending in a first direction X,

a p doped second base layer 8, which is arranged between the first baselayer 9 and the emitter electrode 3, which second base layer 8 is indirect electrical contact to the emitter electrode 3, which second baselayer 8 has a higher doping concentration than the first base layer 9,which second base layer 8 extends perpendicularly deeper than the sourceregion while allowing the horizontal channels to form,

an n doped source region 7, which is arranged at the emitter side 31embedded into the first base layer 9 and contacts the emitter electrode3, which source region 7 has a higher doping concentration than thedrift layer 4, and extends in a first direction X

a first gate electrode 10, which is arranged on top of the emitter side31 and the first gate electrode 10 is electrically insulated from thefirst base layer 9, the source region 7 and the drift layer 4 by a firstinsulating layer 12, an lateral/horizontal channel 15 is formablebetween the emitter electrode 31, the source region 7, the first baselayer 9 and the drift layer 4,

a plurality of trenches embedding second gate electrodes 11, each ofwhich is electrically insulated from the first base layer 9, and thedrift layer 4 by a second insulating layer 12′ and which trenches arearranged with their length parallel to the third dimension Z (ie.orthogonally to the top view extension direction of the first base layer9), and is discontinued in the planar channel regions 15 and extendsdeeper into the drift layer 4 than the first base layer 9, a verticalchannel is formable between the lateral/horizontal channel, the firstbase layer 9 and the drift layer 4,

a collector layer 6 arranged between the buffer layer 5 and thecollector electrode 2, which collector layer 6 is in direct electricalcontact to the collector electrode 2, and

a buffer layer 5 arranged between the collector layer 6 and the driftregion 4.

The trench regions can be better viewed in the top cell view shown inFIG. 11 for the first main embodiment of the inventive design. Theinventive design consists of a basic planar MOS cell design with activetrenches 11 (connected to gate electrode 10) occupying the regionsbetween the planar cells in the 3^(rd) dimension, or in other words,orthogonal to the extension direction of the planar cells in the firstdimension. FIG. 12 to FIG. 14 show the cross sections of the inventivedesign along the cut lines shown in FIG. 11. The inventive designprovides a lateral/horizontal channel 15 in the planar regions 10 (A-A′)and a lateral/horizontal channel 15 with improved vertical spreading atthe edge of the trench region 11 (B-B′), and exceptionally, a seriesconnection between a planar lateral/horizontal channel and a verticalchannel in the trench region 11 (C-C′).

Specifically, the trenches extend in a second dimenstion to a depthapproximately in a range from about 2 μm to about 7 μm from the topside. The trench width may range from about 3 μm to about 0.5 μm.

With respect to the top views shown in FIG. 15A-B, the critical designaspects are the dimension W_(t) or mesa between the orthogonal trenchesin the first direction, as well as the dimension W_(p) representing thedistance from the end of one trench to the adjacent trench in the thirddimension. Improved carrier storage/reduced hole drainage is expected asthe dimensions W_(t) and W_(p) are reduced. The value of W_(t) may be ina range from about 5 μm to below 0.1 μm, more preferably from 1 μm to0.1 μm—which is achievable with the proposed design because noadditional structures have to be lithographically defined in between thetrenches, as in prior art. Also, improved carrier storage/reduced holedrainage is expected with reducing the planar cell dimensions, or bykeeping the same pitch for the planar cell part, but reducing thedistance W_(p) by etching the adjacent trenches closer to each other.More specifically, W_(p) could extend approximately in a range fromabout 20 μm to about 1 μm, preferably from 5 μm to 1 μm, and morepreferably from 2 μm to 1 μm. The length of the orthogonal trenches canvery on the same structure as shown in FIG. 15B where the trenches witha shorter length 11′ can be discontinued in the drift region 4, and thetrenches with longer length 11 can be discontinued in the first baselayer 9. Other orthogonal trench design parameters can also vary on thesame structure such as the width, depth or voltage bias. For example,some trenches could be etched at a larger depth than adjacent ones, orwith a different width.

The inventive method for manufacturing a planar MOS cell on an emitterside is shown in cross sections in the FIGS. 16 to 24 and correspondingtop views in the FIGS. 25 to 31. The method comprises manufacturingsteps as follows.

As shown in FIG. 16 (corresponding top view FIG. 25) the method isstarted with a lightly n doped substrate 4, which has an emitter side31. As shown in FIG. 17 (top view FIG. 26), a trench region 11 isproduced by dry etching through a mask opening 111 into the substrate 4.A first oxide layer 12 and second oxide layer 12′ are producedcompletely covering the substrate 4 on the emitter side 31. As shown inFIG. 18 (top view FIG. 27), electrically conductive layers 10 and 11 areproduced on top of the first oxide layer 12 and second oxide layer 12′respectively. The electrically conductive layers 10 and 11 cover thefirst oxide layer 12 and second oxide layer 12′ completely. According toFIG. 19 and FIG. 20 (top view FIG. 28) an opening 101 in form of athrough hole is etched in the electrically conductive layer 10,resulting in a structured gate electrode layer 10.

Afterwards, the first dopants of p conductivity type are implanted intothe substrate 4 (shown by arrows 90 in FIG. 20) (top view FIG. 29) usingthe structured gate electrode layer with its opening as a mask,resulting in a first implant region 9. Afterwards, the implanted firstdopants are diffused into the substrate 4 as shown in FIG. 21 (top viewFIG. 29). The first dopants are preferably Boron ions. The first dopantsare preferably implanted with an energy of 20-100 keV and/or a dose of5×10¹³/cm² to 2×10¹⁴/cm². The first dopants are driven into a maximumdepth between 1 μm and 5 μm, in particular between 1 and 3 μm and inparticular between 1 and 2 μm. As shown in FIG. 21, the first dopantsare not only driven into the substrate 4 in a direction perpendicular tothe surface, but they are spread out laterally as shown in top view FIG.29, and will reach the orthogonal trenches 11 to form the seriesconnected planar and trench channels 15 and 16, while reaching outfurther laterally in the mesa region between the orthogonal trenches 11to form only the planar channel 15.

Afterwards, the second dopants of highly doped n conductivity type areimplanted 70 into the substrate 4 through a mask or using the structuredgate electrode layer with its opening as a mask, resulting in a secondimplant region 7. Afterwards, the implanted second dopants are diffusedinto the substrate 4. The second dopants are preferably Phosphorous orArsenic preferably Arsenic ions. The second dopants are preferablyimplanted with an energy of 100-160 keV and/or a dose of 1×10¹⁵/cm² to1×10¹⁶/cm². The second dopants are driven into a maximum depth between0.5 μm and 1 μm. As shown in FIG. 22 (top view FIG. 30), the seconddopants are mainly driven into the substrate 4 in a directionperpendicular to the surface, but they are only slightly spread outlaterally to form the critical source region under the gate oxide.

Afterwards, the third dopants of highly doped p conductivity type areimplanted 80 into the substrate 4 through a mask opening or using thestructured gate electrode layer with its opening as a mask, resulting ina third implant region 8. Afterwards, the implanted third dopants arediffused into the substrate 4. The third dopants are preferably Boronions. The third dopants are preferably implanted to a higher depth thanthe second region with an energy of 50-160 keV and/or a dose of1×10¹⁵/cm² to 1×10¹⁶/cm². The third dopants are driven into a maximumdepth between 0.5 μm and 2.5 μm. As shown in FIG. 22 (top view FIG. 30),the third dopants are mainly driven into the substrate 4 in a directionperpendicular to the surface, but they are only slightly spread outlaterally to cover a section or all the lower part of the second regionand ensure a lateral/horizontal channel can be formed in the planarcell.

Afterwards, an insulating oxide layer 13 is produced to cover the firstmain side 31 completely. The insulating oxide layer thickness can rangebetween 500 nm to 1500 nm. A contact opening 14 is then produced by dryetching the insulating oxide layer 13 fully through a mask opening 121as shown in FIG. 22 to reach the third dopants region 8 as shown in FIG.23 (top view FIG. 31). The contact opening 14 is filled with metal toproduce a direct electrical emitter contact 3 to the second dopantsregion 7 and third dopants region 8 as shown in FIG. 24.

A second exemplary embodiment consists of a second base layer 8 extendedunder the source region, together with an etched contact through thesource region 7 to reach the second base layer 8 as shown in FIG. 32.The advantage of the second exemplary embodiment is that it does notrequire the use of the additional masks to structure the source region 7and second base region 8.

The inventive design is also suitable for a reverse conducting structureby introducing n type dopants at the collector side to produce collectorshorts 18, and an internal anti-parallel diode structure as shown inFIG. 33.

An enhancement layer or fourth dopants of lightly doped n conductivitytype can be implanted and diffused before the first dopants implant asshown in FIG. 34. The fourth dopants of n conductivity type areimplanted into the substrate 4 using the structured gate electrode layerwith its opening as a mask, resulting in a fourth implant region 17.Afterwards, the implanted fourth dopants are diffused into the substrate4. The fourth dopants are preferably Phosphorous ions. The fourthdopants are preferably implanted with an energy of 20-100 keV and/or adose of 5×10¹²/cm² to 5×10¹³/cm². The fourth dopants are driven into amaximum depth between 2 μm and 8 μm, in particular between 2 and 6 μmand in particular between 2 and 4 μm. As shown in FIG. 34, the fourthdopants are not only driven into the substrate 4 in a directionperpendicular to the surface, but they are spread out laterally.

It is possible to apply the invention to a method for the manufacturingof semiconductor devices, in which the conductivity type of all layersis reversed, i.e. with a lightly p doped substrate etc.

REFERENCE LIST

-   1: inventive planar MOS cell power semiconductor device-   3: emitter metallization (electrode)-   31: emitter side-   2: collector metallization (electrode)-   21: collector side-   4: drift layer, substrate-   5: buffer layer-   6: collector layer-   7: n-doped source layer-   8: p-doped second base layer-   9: p-doped first base layer-   10: planar gate electrode, electrically conductive layer-   10′: uncovered gate electrode-   11: trench gate electrode, electrically conductive layer-   11′: trench region gate electrode with different dimensions-   12: insulating gate oxide for planar gate-   12′: insulating gate oxide for trench gate-   13: insulation layer for planar cell and trench cell-   14: emitter contact opening-   15: horizontal channel for planar gate-   16: vertical channel for trench gate-   17: enhancement layer-   18: collector shorts-   70: source implantation step-   80: second base implantation step-   90: first base implantation step-   100: electrically conductive layer etch mask-   110: electrically conductive layer etch mask opening-   111: trench etch mask opening-   120: contact etch mask-   121: contact etch mask opening-   200: planar MOS cell power semiconductor device (prior art)-   300: trench MOS cell power semiconductor device (prior art)-   400: trench planar MOS cell power semiconductor device (prior art)-   401: trench planar MOS cell power semiconductor device (prior art)-   500: trench planar MOS cell power semiconductor device (prior art)-   600: trench planar MOS cell power semiconductor device (prior art)-   700: trench planar MOS cell power semiconductor device (prior art)-   800: planar MOS cell power semiconductor device (prior art)

1. A power semiconductor, comprising an emitter side and a collectorside separated in a second dimension, wherein an emitter electrode isoperatively connected to the emitter side and a collector electrode isoperatively connected to the collector side, and wherein the powersemiconductor device further comprises: a drift layer of a firstconductivity type, arranged between the emitter side and the collectorside; a first base layer of a second conductivity type, arranged betweenthe drift layer and the emitter electrode, which first base layerextends longitudinally in a first dimension in a top view plane; asource region of the first conductivity type with a higher dopingconcentration than the drift layer embedded within the first base layerat the emitter side, wherein the source region contacts the emitterelectrode and extends longitudinally in the first direction, andlaterally in a third dimension to a first gate electrode; a second baselayer of the second conductivity type with a higher doping concentrationthan the first base layer, embedded within the first base layer at theemitter side extending deeper than the source region in the seconddimension, wherein the second base layer contacts the emitter electrodethrough a contact opening; a first gate electrode, arranged on top ofthe emitter side and electrically insulated from the first base layer,the source region and the drift layer by a first insulating layer,wherein a lateral/horizontal channel is formed between the emitterelectrode, the source region, the first base layer and the drift layerwhen a positive gate bias is applied to the first gate electrode; and aplurality of trenches embedding second gate electrodes, eachelectrically insulated from the first base layer and the drift layer bya second insulating layer and with their length parallel to the thirddimension, and each extends deeper than the first base layer in thesecond direction, wherein a vertical channel is formed between thelateral/horizontal channel, the first base layer and the drift layer,when a positive gate bias is applied to the second gate electrodes.
 2. Apower semiconductor according to claim 1, wherein: the first base isshaped with stripes with their length parallel to the first dimension,and their width parallel to the third dimension in a top view plane thetrenches are shaped with stripes in another direction orthogonal to thestripes of the first base layer, the stripes of the trenches are dividedinto rectangles spaced apart from each other by the stripes of the firstbase layer.
 3. A power semiconductor according to claim 1, wherein thefirst and second gate electrodes are electrically connected.
 4. A powersemiconductor according to claim 1, wherein at least a portion of thesecond gate electrodes are electrically connected to the emitterelectrode.
 5. A power semiconductor according to claim 1, wherein atleast a portion of the second gate electrodes are electrically floating.6. A power semiconductor according to claim 1, further comprising abuffer layer of the first conductivity type with a higher dopingconcentration than the drift layer, arranged between the drift layer andthe collector electrode.
 7. A power semiconductor according to claim 1,further comprising: a collector layer of the second conductivity typearranged on the collector side between the drift layer and the collectorelectrode; and/or a buffer layer of the first conductivity type with ahigher doping concentration than the drift layer arranged on thecollector side between the drift layer and the collector electrode.
 8. Apower semiconductor according to claim 7, further comprising a reverseconducting type device with a collector short layer of the firstconductivity type arranged at the collector side between the collectorelectrode and the buffer layer.
 9. A power semiconductor according toclaim 1 wherein a dopant of the first base comprises Boron ions.
 10. Apower semiconductor according to claim 1, wherein a dopant of the sourceregion comprises Phosphorous or Arsenic ions.
 11. A power semiconductoraccording to claim 1, wherein a dopant of the second base comprisesBoron ions, wherein the dopant at least partially covers a lower part ofthe source region while ensuring that the lateral/horizontal channel isformed between the emitter electrode, the source region, the first baselayer and the drift layer when a positive voltage bias is applied to thefirst gate electrode.
 12. A power semiconductor according to claim 1,wherein a carrier enhancement layer of the first conductivity typeseparates the drift layer and the first base layer.
 13. A powersemiconductor according to claim 12, wherein a dopant of the carrierenhancement layer comprises Phosphorous ions.
 14. A power semiconductoraccording to claim 1, wherein a distance between a second wall of atrench recess and a first wall of an adjacent trench in the firstdimension is below 5 μm.
 15. A power semiconductor according to claim 1,wherein a distance between adjacent trenches in the third dimensionextends from about 20 μm to about 1 μm.
 16. A power semiconductoraccording to claim 1, wherein the power semiconductor has a stripelayout design or cellular layout design.
 17. A method for manufacturinga power semiconductor, the method comprising: forming a drift layer froma lowly doped wafer of a first conductivity type, the drift layer havingan emitter side and a collector sider; applying a mask and etching atrench recess on a first main side of a substrate of a firstconductivity type; forming a first oxide layer on a first main side ofthe substrate of the first conductivity type; producing a structuredgate electrode layer with at least one opening on the first main side ontop of the first oxide layer; using the structured gate electrode layeron the first main side as a mask for implanting a first dopant of asecond conductivity type, different from the first conductivity type,into the substrate on the first main side; diffusing the first dopantsinto the substrate forming a well; using the structured gate electrodelayer on the first main side as a mask for implanting second dopants ofthe first conductivity type into the substrate on the first main side;diffusing the second dopants to a lower depth than the first dopants forforming a source contact; using the structured gate electrode layer toimplant third dopants of the second conductivity type into the substrateon the first main side to a depth higher than the second dopants;diffusing the third dopants into the substrate, wherein the thirddopants are diffused to a lower depth than the first dopants; andforming a second insulating layer on the first main side of thesubstrate; etching a contact opening through the insulating layer andthe second dopants and filling a resulting contact opening with metal.18. The method for manufacturing a power semiconductor according toclaim 17, wherein the first dopants are implanted with an energy of20-100 keV and/and a dose of 5×10¹³/cm² to 2×10¹⁴/cm².
 19. The methodfor manufacturing a power semiconductor according to claim 17, whereinthe second dopants are implanted with an energy of 100-160 keV and/and adose of 1×10¹⁵/cm² to 1×10¹⁶/cm².
 20. The method for manufacturing apower semiconductor according to claim 17, wherein the third dopants areimplanted with an energy of 100-160 keV and a dose of 1×10¹⁵/cm² to1×10¹⁶/cm².
 21. The method for manufacturing a power semiconductoraccording to claim 17, further comprising implanting fourth dopantsthrough a same mask layer as the first dopants to form a carrierenhancement layer, the fourth dopants have an energy of 20-100 keV and adose of 5×10¹²/cm² to 5×10¹³/cm², and wherein the fourth dopants arediffused before the first dopants are implanted.
 22. A method formanufacturing a power semiconductor, the method comprising: providing alowly doped wafer of a first conductivity type having an emitter sideand a collector side, wherein the lowly doped wafer comprises asubstrate, and forming a drift layer; applying a mask and etching atrench recess on the first main side of the substrate of a firstconductivity type; forming a first oxide layer on a first main side ofthe substrate of the first conductivity type; producing a structuredgate electrode layer with at least one opening on the first main side ofthe substrate on top of the first oxide layer; using the structured gateelectrode layer on the first main side of the substrate as a mask forimplanting a first dopant of a second conductivity type, different thanthe first conductivity type, into the first main side of the substrate;diffusing the first dopants into the substrate to form a well; applyinganother mask and using the other mask together with the structured gateelectrode layer on the first main side as a mask for implanting seconddopants of the first conductivity type into the substrate on the firstmain side; diffusing the second dopants to a lower depth than the firstdopants to form a source contact; applying still another mask and usingthe still other mask together with the structured gate electrode layerfor implanting third dopants of the second conductivity type into thesubstrate on the first main side to a depth higher than the seconddopants; diffusing the third dopants into the substrate to a lower depththan the first dopants; forming a second insulating layer on the firstmain side of the substrate; and etching a contact opening through theinsulating layer and filling a resulting contact opening with metal. 23.The method for manufacturing a power semiconductor according to claim22, wherein the first dopants are implanted with an energy of 20-100 keVand/and a dose of 5×10¹³/cm² to 2×10¹⁴/cm².
 24. The method formanufacturing a power semiconductor according to claim 22, wherein thesecond dopants are implanted with an energy of 100-160 keV and/and adose of 1×10¹⁵/cm² to 1×10¹⁶/cm².
 25. The method for manufacturing apower semiconductor according to claim 22, wherein the third dopants areimplanted with an energy of 100-160 keV and a dose of 1×10¹⁵/cm² to1×10¹⁶/cm².
 26. The method for manufacturing a power semiconductoraccording to claim 22, further comprising implanting fourth dopantsthrough a same mask layer as the first dopants to form a carrierenhancement layer, the fourth dopants have an energy of 20-100 keV and adose of 5×10¹²/cm² to 5×10¹³/cm², and wherein the fourth dopants arediffused before the first dopants are implanted.